The present invention relates to an output buffer of semiconductor memory device with high integration, which externally produces a sensed cell data, in particularly to an output buffer for preventing a shifting delay of an output signal by presetting the output of the output buffer.
FIG. 1 is a circuit diagram of a conventional output buffer, which is composed of a driver unit 10 and a logic circuit unit 12. The driver unit 10 is composed of a pull-up transistor(PMOS transistor, PM) for pulling-up the output node N1, a pull-down transistor(NMOS transistor, NM) for pulling-down the output node N1. The logic circuit unit 12 controls the pull-up and the pull-down transistors PM and NM based on the logic combination of a data /DATA to be outputted and an output enable signal OE.
Here, the logic circuit unit 12 is composed of an inverter IV1 for receiving the data /DATA so as to invert it, a NAND gate NAG1 for performing a logic-NAND operation with respect to the output enable signal OE and the data DATA produced from the inverter IV1, and a NOR gate NOG1 for performing a logic-NOR operation with respect to the data DATA from the inverter IV1 and an inverted output enable signal /OE.
The operation of the output buffer of semiconductor memory device as above are as follows.
In case the output enable signal OE is low, the output of the NAND gate NAG1 is high level which is, in turn, applied to the gate of the pull-up transistor PM, and the output of the NOR gate NOG1 is low level which is, in turn, applied to the gate of the pull-down transistor NM. As a result, the pull-up transistor PM and the pull-down transistor NM are turned off so that the output node is floating.
Meanwhile, in case the output enable signal OE is high, the outputs of the NAND gate NAG1 and the NOR gate NOG1 are determined based on the logic level of the data DATA produced from the inverter IV1. That is, when the data DATA is low level, the output of the NAND gate NAG1 is high level which is applied to the gate of the pull-up transistor PM so as to be turned off. In addition, the gate of the pull-down transistor NM is applied with the high level signal from the NOR gate NOG1, so that the pull-down transistor NM is turned on to pull-down the output node N1 which produces a low level signal.
Alternatively, when the data DATA is high level, the NAND gate NAG1 produces a low level signal which is applied to the gate of the pull-up transistor PM, and the NOR gate NOG1 produces a low level signal which is applied to the gate of the pull-down transistor NM. Thus, the pull-up transistor PM is turned on and the pull-down transistor NM is turned off, so that the output node N1 is driven by pulling-up operation of the pull-up transistor PM and the high level signal is outputted.
The conventional output buffer as above, however, has a problem that the output signal OUT is fully swung between a ground level and a power supply voltage level, which causes the delay of the output signal changeover due to the deep swing voltage depth, thereby reducing the overall operation speed. Also, an output noise is generated due to the current flowing therein in order to drive an capacitor(which serves as a load) coupled in general to the output node of the output buffer, so that the other circuits may be malfunctioned.